Maxim-Integrated /max32520 /GCR /RST0

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Interpret as RST0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DMA)DMA 0 (WDT0)WDT0 0 (GPIO0)GPIO0 0 (GPIO1)GPIO1 0 (TMR0)TMR0 0 (TMR1)TMR1 0 (TMR2)TMR2 0 (TMR3)TMR3 0 (UART0)UART0 0 (SPI0)SPI0 0 (SPI1)SPI1 0 (I2C0)I2C0 0 (CRYPTO)CRYPTO 0 (SOFT)SOFT 0 (PERIPH)PERIPH 0 (SYS)SYS

Description

Reset.

Fields

DMA

DMA Reset.

WDT0

Watchdog Timer Reset.

GPIO0

GPIO0 Reset. Setting this bit to 1 resets GPIO0 pins to their default states.

GPIO1

GPIO1 Reset. Setting this bit to 1 resets GPIO1 pins to their default states.

TMR0

Timer0 Reset. Setting this bit to 1 resets Timer 0 blocks.

TMR1

Timer1 Reset. Setting this bit to 1 resets Timer 1 blocks.

TMR2

Timer2 Reset. Setting this bit to 1 resets Timer 2 blocks.

TMR3

Timer3 Reset. Setting this bit to 1 resets Timer 3 blocks.

UART0

UART0 Reset. Setting this bit to 1 resets all UART 0 blocks.

SPI0

SPI0 Reset. Setting this bit to 1 resets all SPI 0 blocks.

SPI1

SPI1 Reset. Setting this bit to 1 resets all SPI 1 blocks.

I2C0

I2C0 Reset.

CRYPTO

Cryptographic Reset. Setting this bit to 1 resets the AES block, the SHA block and the DES block.

SOFT

Soft Reset. Setting this bit to 1 resets everything except the CPU and the watchdog timer.

PERIPH

Peripheral Reset. Setting this bit to 1 resets all peripherals. The CPU core, the watchdog timer, and all GPIO pins are unaffected by this reset.

SYS

System Reset. Setting this bit to 1 resets the CPU core and all peripherals, including the watchdog timer.

Links

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