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Maxim-Integrated /max32520 /GPIO0 /PDPU_SEL0

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Interpret as PDPU_SEL0

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (impedance)GPIO_PDPU_SEL0

GPIO_PDPU_SEL0=impedance

Description

GPIO Input Mode Config 1. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port.

Fields

GPIO_PDPU_SEL0

The two bits in GPIO_PDPU_SEL0 and GPIO_PDPU_SEL1 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode.

0 (impedance): High Impedance.

1 (pu): Weak pull-up mode.

2 (pd): weak pull-down mode.

Links

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Register Reference

https://github.com/analogdevicesinc/msdk