Maxim-Integrated /max32520 /SMON /INTSCN

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as INTSCN

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (dis)SHIELD_EN 0 (dis)TEMP_EN 0 (dis)VBAT_EN 0 (DFD_EN)DFD_EN 0 (DFD_NMI)DFD_NMI 0 (DFD_STDBY)DFD_STDBY 0 (PUF_TRIM_ERASE)PUF_TRIM_ERASE 0 (neg50C)LOTEMP_SEL 0 (dis)VCORELOEN 0 (dis)VCOREHIEN 0 (dis)VDDLOEN 0 (dis)VDDHIEN 0 (dis)VGLEN 0 (unlocked)LOCK

VCORELOEN=dis, VGLEN=dis, VDDHIEN=dis, VDDLOEN=dis, VBAT_EN=dis, VCOREHIEN=dis, LOTEMP_SEL=neg50C, TEMP_EN=dis, SHIELD_EN=dis, LOCK=unlocked

Description

Internal Sensor Control Register.

Fields

SHIELD_EN

Die Shield Enable.

0 (dis): Disable.

1 (en): Enable.

TEMP_EN

Temperature Sensor Enable.

0 (dis): Disable.

1 (en): Enable.

VBAT_EN

Battery Monitor Enable.

0 (dis): Disable.

1 (en): Enable.

DFD_EN

Digital Fault Dector Enable

DFD_NMI

Digital Fault NMI Enable

DFD_STDBY

Digital Fault Dector Stand by Enable

PUF_TRIM_ERASE

Erase puf trim Enable

LOTEMP_SEL

Low Temperature Detection Select.

0 (neg50C): -50 degrees C.

1 (neg30C): -30 degrees C.

VCORELOEN

VCORE Undervoltage Detect Enable.

0 (dis): Disable.

1 (en): Enable.

VCOREHIEN

VCORE Overvoltage Detect Enable.

0 (dis): Disable.

1 (en): Enable.

VDDLOEN

VDD Undervoltage Detect Enable.

0 (dis): Disable.

1 (en): Enable.

VDDHIEN

VDD Overvoltage Detect Enable.

0 (dis): Disable.

1 (en): Enable.

VGLEN

Voltage Glitch Detection Enable.

0 (dis): Disable.

1 (en): Enable.

LOCK

Lock Register. Once locked, the INTSCN register can no longer be modified. Only a battery disconnect will clear this bit. VBAT powers this register.

0 (unlocked): Unlocked.

1 (locked): Locked.

Links

()