data_align=lsb_justified, ref_scale=div1, refbuf_pwr=refbuf_off, pwr=adc_off, clk_en=dis, input_scale=div1, start=inactive, ref_sel=bandgap, ch_sel=ain0
ADC Control
| start | Start ADC Conversion 0 (inactive): undefined 1 (start): undefined |
| pwr | ADC Power Up 0 (adc_off): undefined 1 (adc_on): undefined |
| refbuf_pwr | ADC Reference Buffer Power Up 0 (refbuf_off): undefined 1 (refbuf_on): undefined |
| ref_sel | ADC Reference Select 0 (bandgap): undefined 1 (vdd_div2): undefined |
| ref_scale | ADC Reference Scale 0 (div1): undefined 1 (div2): undefined |
| input_scale | ADC Scale 0 (div1): undefined 1 (div2): undefined |
| clk_en | ADC Clock Enable 0 (dis): undefined 1 (en): undefined |
| ch_sel | ADC Channel Select 0 (ain0): undefined 1 (ain1): undefined 2 (ain2): undefined 3 (ain3): undefined 4 (ain0_div5): undefined 5 (ain1_div5): undefined 6 (vddb_div4): undefined 7 (vdda): undefined 8 (vcore): undefined 9 (vrtc_div2): undefined 10 (rsv_0xa): undefined 11 (vddio_div4): undefined 12 (vddioh_div4): undefined |
| data_align | ADC Data Alignment Select 0 (lsb_justified): undefined 1 (msb_justified): undefined |