CLK_EDGE_SEL=RISING, CLK_ACTIVE=ALWAYS, VSYNC_POL=ACTIVELO, HSYNC_POL=ACTIVELO, VDEN_POL=ACTIVELO
LCD Clock Control Register
| LCD_CLKDIV | Clock divsor |
| STN_AC_BIAS | AC Bias Frequency Control. THis fiels sets the AC Bias Frequency output on the CLCD_VDEN pin for Color StN display mode. |
| VDEN_POL | CLCD_VDEN Polarity Selection. This field sets the polarity of the video enable signal output pin. 0 (ACTIVELO): Active Low 1 (ACTIVEHI): Active High |
| VSYNC_POL | VSYNC Polarity Selection. This field sets the polarity of the vertical sync signal output pin. 0 (ACTIVELO): Active Low 1 (ACTIVEHI): Active Hi |
| HSYNC_POL | HSYNC Polarity Selection. This field sets the polarity of the horizontal sync signal output pin. 0 (ACTIVELO): Active Low 1 (ACTIVEHI): Active Hi |
| CLK_EDGE_SEL | Clock Edge Selection. This field controls the clock edge that is used by the LCD panel to sample the data and signal lines. 0 (RISING): Rising edge 1 (FALLING): Falling Edge |
| CLK_ACTIVE | Clock Active on Data. If the display type is Color STN 8-bit, this bit selects if the CLCD_CLK output is active always or only during data output to the display. 0 (ALWAYS): Always Active 1 (ONDATA): ACTIVE ON DATA |