VCI_SEL=ON_VSYNC, PWR_ENABLE=LO, LEND_POL=ACTIVELO, COMPACT_24b=1_PFR, BPP=BPP1, MODE565=BGR556, BURST_SIZE=4WORDS, ENDIAN=LBLP, CLCD_ENABLE=dis
LCD Control Register
| CLCD_ENABLE | LCD Enable 0 (dis): Disable 1 (en): Enable |
| VCI_SEL | Vertical Compare Interrupt Source Select 0 (ON_VSYNC): On Vertical Sync 1 (ON_VBP): On Vertical Back Porch 2 (ON_VDEN): On Active Video 3 (ON_VFP): On Vertical Front Porch |
| DISPTYPE | Display Type 4 (8BITCOLORSTN): STN Color 8 bit 8 (TFT): TFT |
| BPP | BPP 0 (BPP1): BPP 1 1 (BPP2): BPP 2 2 (BPP4): BPP 4 3 (BPP8): BPP 8 4 (BPP16): BPP 16 5 (BPP24): BPP 24 |
| MODE565 | MODE565 0 (BGR556): MODE 556 1 (RGB565): MODE 565 |
| ENDIAN | EMODE 0 (LBLP): LLBP 1 (BBBP): BBBP 2 (LBBP): LBBP 3 (RFU): RFU |
| COMPACT_24b | C24 0 (1_PFR): 1 pixel per frame buffer entry 1 (1ANDA3RD_PFR): 1 and 1/3 pixels per fram buffer entry |
| BURST_SIZE | BURST 0 (4WORDS): 4 32-bit words. 1 (8WORDS): 8 32-bit words. 2 (16WORDS): 16 32-bit words. |
| LEND_POL | LEND Polarity Selection. This field sets the polarity of the line end signal output pin. 0 (ACTIVELO): Active Low 1 (ACTIVEHI): Active High |
| PWR_ENABLE | Display Power Enable. Enables power to the display using the PWREN output pin. 0 (LO): Power enable pin is set low. 1 (HI): Power enable pin is set high. |