CCD=non_div, SYSOSC_RDY=busy, SYSOSC_SEL=CRYPTO, SYSCLK_PRESCALE=div1
Clock Control.
| SYSCLK_PRESCALE | Prescaler Select. This 3 bit field sets the system operating frequency by controlling the prescaler that divides the output of the PLL0. 0 (div1): Divide by 1. 1 (div2): Divide by 2. 2 (div4): Divide by 4. 3 (div8): Divide by 8. 4 (div16): Divide by 16. 5 (div32): Divide by 32. 6 (div64): Divide by 64. 7 (div128): Divide by 128. |
| SYSOSC_SEL | Clock Source Select. This 3 bit field selects the source for the system clock. 0 (CRYPTO): Internal Primary Oscilatior Clock 2 (HFXIN): 24MHz Internal Oscillator is used for the system clock. 3 (NANORING): 8kHz Internal Nano Ring Oscillator is used for the system clock. 4 (HIRC96): 120 MHz Internal Oscillator. 5 (HIRC8): Internal 7.3728MHz oscillator. 6 (X32K): External 32KHz oscillator. |
| SYSOSC_RDY | Clock Ready. This read only bit reflects whether the currently selected system clock source is running. 0 (busy): Switchover to the new clock source (as selected by CLKSEL) has not yet occurred. 1 (ready): System clock running from CLKSEL clock source. |
| CCD | Cryptographic clock divider 0 (non_div): The cryptographic accelerator clock is running in non-divided mode. 1 (div): The cryptographic accelerator clock is running in divided mode. |
| X32K_EN | 32KHz External Clock Enable. |
| CRYPTO_EN | 50MHz High Frequency Internal Reference Clock Enable. |
| HIRC96_EN | 120MHz High Frequency Internal Reference Clock Enable. |
| HIRC8_EN | 7.3728MHz High Frequency Internal Reference Clock Enable. |
| HIRC8_VS | 7.3728MHz Internal Oscillator Voltage Source Select |
| X32K_RDY | 32KHz External Oscillator Ready. |
| CRYPTO_RDY | 50MHz Internal Oscillator Ready. |
| HIRC96_RDY | 120MHz Internal Oscillator Ready. |
| HIRC8_RDY | 7.3728MHz Internal Oscillator Ready. |
| NANORING_RDY | Internal Nano Ring Oscillator Low Frequency Reference Clock Ready. |