Maxim-Integrated /max32650 /GCR /EVENT_EN

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Interpret as EVENT_EN

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (dis)DMAEVENT 0 (dis)RXEVENT 0 (dis)TXEVENT

DMAEVENT=dis, TXEVENT=dis, RXEVENT=dis

Description

Event Enable Register.

Fields

DMAEVENT

Enable DMA event. When this bit is set, a DMA event will cause an RXEV event to wake the CPU from WFE sleep mode.

0 (dis): DMA CTZ Event will not wake up the device.

1 (en): DMA CTZ Event Wake-up Enabled.

RXEVENT

Enable RXEV pin event. When this bit is set, a logic high of GPIO0[24] will cause an RXEV event to wake the CPU from WFE sleep mode.

0 (dis): A receive event is not generated when an external input transitions from low to high.

1 (en): A receive event is generated when external event is triggered.

TXEVENT

Enable TXEV pin event. When this bit is set, TXEV event from the CPU is output to GPIO[25].

0 (dis): Transmit event disabled.

1 (en): A transmit event is enabled on Send Event instruction.

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