AONDIV=div4, SDHCFRQ=60M
Peripheral Clock Divider.
| SDHCFRQ | This bit selects the frequency of the SDHC clock. If set, the clock oscillates at 50Mhz, otherwise it will oscillate at 60MHz. 0 (60M): SDHC Freq = 120MHz/2. 1 (50M): SDHC Freq = 50Mhz. |
| ADCFRQ | ADC Clock divider. ADC Clock Frequency = Periph_Clock/adcfrq. Values 0 and 1 invalid. 2 (div2): ADC Freq = Periph_Clock/2. 3 (div3): ADC Freq = Periph_Clock/3. 4 (div4): ADC Freq = Periph_Clock/4. 5 (div5): ADC Freq = Periph_Clock/5. 6 (div6): ADC Freq = Periph_Clock/6. 7 (div7): ADC Freq = Periph_Clock/7. 8 (div8): ADC Freq = Periph_Clock/8. 9 (div9): ADC Freq = Periph_Clock/9. 10 (div10): ADC Freq = Periph_Clock/10. 11 (div11): ADC Freq = Periph_Clock/11. 12 (div12): ADC Freq = Periph_Clock/12. 13 (div13): ADC Freq = Periph_Clock/13. 14 (div14): ADC Freq = Periph_Clock/14. 15 (div15): ADC Freq = Periph_Clock/15. |
| AONDIV | Always-ON (AON) domain CLock Divider. These bits define the AON domain clock divider. 0 (div4): PCLK divide by 4. 1 (div8): PCLK divide by 8. 2 (div16): PCLK divide by 16. 3 (div32): PCLK divide by 32. |