CCHK=complete, DCACHE_FLUSH=normal, OVR=0v9, BSTAPEN=dis, CHKRES=pass, FLASH_PAGE_FLIP=normal, CCACHE_FLUSH=normal, DCACHE_DIS=enabled
System Control.
| BSTAPEN | Boundary Scan TAP enable. When enabled, the JTAG port is connected to the Boundary Scan TAP. Otherwise, the port is connected to the ARM ICE function. This bit is reset by the POR. Reset value and access depend on the part number. 0 (dis): Boundary Scan TAP port disabled. 1 (en): Boundary Scan TAP port enabled. |
| FLASH_PAGE_FLIP | Flips the Flash bottom and top halves. (Depending on the total flash size, each half is either 256K or 512K). Initiating a flash page flip will cause a flush of both the data buffer on the DCODE bus and the internal instruction buffer. 0 (normal): Physical layout matches logical layout. 1 (flipped): Bottom half mapped to logical top half and vice versa. |
| CCACHE_FLUSH | Code Cache Flush. This bit is used to flush the code caches and the instruction buffer of the Cortex-M4. 0 (normal): Normal Code Cache Operation 1 (flush): Code Caches and CPU instruction buffer are flushed |
| DCACHE_FLUSH | Write 1 to flush the external memory controller’s 16KB cache. This bit is automatically cleared to 0 when the flush is complete. 0 (normal): Normal External Cache Operation 1 (flush): External cache being flushed. |
| DCACHE_DIS | Disable EMCC used for SPIXR or HyperBus/Xccela Bus code and data cache. 0 (enabled): EMCC enabled. 1 (disabled): EMCC disabled and line buffer bypassed. |
| CCHK | Compute ROM Checksum. This bit is self-cleared when calculation is completed. Once set, software clearing this bit is ignored and the bit will remain set until the operation is completed. 0 (complete): No operation/complete. 1 (start): Start operation. |
| CHKRES | ROM Checksum Result. This bit is only valid when CHKRD=1. 0 (pass): ROM Checksum Correct. 1 (fail): ROM Checksum Fail. |
| OVR | These bits select the operating voltage range. 0 (0v9): 0.9V +/- 10%. 1 (1V): 1.0V +/- 10%. 2 (1V1): 1.1V +/- 10%. |