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Maxim-Integrated /max32650 /I2C0 /CLK_HI

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Interpret as CLK_HI

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0SCL_HI

Description

Clock high Register.

Fields

SCL_HI

Clock High. In master mode, these bits define the SCL high period.

Links

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Register Reference

https://github.com/analogdevicesinc/msdk