Maxim-Integrated /max32650 /I2C0 /RX_CTRL0

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Interpret as RX_CTRL0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (respond)DNR 0 (not_flushed)RXFSH 0RXTH

RXFSH=not_flushed, DNR=respond

Description

Receive Control Register 0.

Fields

DNR

Do Not Respond.

0 (respond): Always respond to address match.

1 (dont_respond): Do not respond to address match when RX_FIFO is not empty.

RXFSH

Receive FIFO Flush. This bit is automatically cleared to 0 after the operation. Setting this bit to 1 will affect RX_FIFO status.

0 (not_flushed): FIFO not flushed.

1 (flush): Flush RX_FIFO.

RXTH

Receive FIFO Threshold. These bits define the RX_FIFO interrupt threshold.

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