ACRE=sync, ENABLE=dis, SQWOUT_EN=dis, SSEC_ALARM_EN=dis, SSEC_ALARM_FL=inactive, WRITE_EN=dis, BUSY=idle, TOD_ALARM_EN=dis, TOD_ALARM_FL=inactive, READY_INT_EN=dis, FREQ_SEL=freq1Hz, READY=not_ready
RTC Control Register.
| ENABLE | Real Time Clock Enable. This bit enables the Real Time Clock. This bit can only be written when WE=1 and BUSY =0. Change to this bit is effective only after BUSY is cleared from 1 to 0. 0 (dis): Disable. 1 (en): Enable. |
| TOD_ALARM_EN | Alarm Time-of-Day Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0. 0 (dis): Disable. 1 (en): Enable. |
| SSEC_ALARM_EN | Alarm Sub-second Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0. 0 (dis): Disable. 1 (en): Enable. |
| BUSY | RTC Busy. This bit is set to 1 by hardware when changes to RTC registers required a synchronized version of the register to be in place. This bit is automatically cleared by hardware. 0 (idle): Idle. 1 (busy): Busy. |
| READY | RTC Ready. This bit is set to 1 by hardware when the RTC count registers update. It can be cleared to 0 by software at any time. It will also be cleared to 0 by hardware just prior to an update of the RTC count register. 0 (not_ready): Register has not updated. 1 (ready): Ready. |
| READY_INT_EN | RTC Ready Interrupt Enable. 0 (dis): Disable. 1 (en): Enable. |
| TOD_ALARM_FL | Time-of-Day Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor. 0 (inactive): Not active 1 (Pending): Active |
| SSEC_ALARM_FL | Sub-second Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor. 0 (inactive): Not active 1 (Pending): Active |
| SQWOUT_EN | Square Wave Output Enable. 0 (dis): Disabled. 1 (en): Enabled. |
| FREQ_SEL | Frequency Output Selection. When SQE=1, these bits specify the output frequency on the SQW pin. 0 (freq1Hz): 1 Hz (Compensated). 1 (freq512Hz): 512 Hz (Compensated). 2 (freq4KHz): 4 KHz. |
| ACRE | Asynchronous Counter Read Enable. 0 (sync): SEC and SSEC registers synchronized and should only be accessed while CTRL.rdy = 1. 1 (async): SEC and SSEC registers are asynchronous and will require software interaction to ensure data accuracy. |
| WRITE_EN | Write Enable. This register bit serves as a protection mechanism against unintentional writes to critical RTC bits. 0 (dis): Writes to RTC_CTRL.enable are ignored. 1 (en): Writes to RTC_CTRL.enable are allowed. |