Maxim-Integrated /max32650 /SDHC /CFG_0

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Interpret as CFG_0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0TO_FREQ0 (CLK_UNIT)CLK_UNIT 0CLK_FREQ0MAX_BLK_LEN 0 (8_BIT)8_BIT 0 (ADMA2)ADMA2 0 (HS)HS 0 (SDMA)SDMA 0 (SUSPEND)SUSPEND 0 (3_3V)3_3V 0 (3_0V)3_0V 0 (1_8V)1_8V 0 (64_BIT_SYS_BUS)64_BIT_SYS_BUS 0 (ASYNC_INT)ASYNC_INT 0SLOT_TYPE

Description

Capabilities 0-31.

Fields

TO_FREQ

Timeout Clock Frequency.

1 (1mhz): undefined

CLK_UNIT

Timeout Clock Unit.

CLK_FREQ

Base Clock Frequency For SD Clock.

MAX_BLK_LEN

Max Block Length.

2 (2048_bytes): undefined

8_BIT

8-bit Support for Embedded Device.

ADMA2

ADMA2 Support.

HS

High Speed Support.

SDMA

SDMA Support.

SUSPEND

Suspend/Resume Support.

3_3V

Voltage Support 3.3V.

3_0V

Voltage Support 3.0V.

1_8V

Voltage Support 1.8V.

64_BIT_SYS_BUS

64-bit System Bus Support.

ASYNC_INT

Asynchronous Interrupt Support.

SLOT_TYPE

Slot Type.

Links

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