Maxim-Integrated /max32650 /SDHC /ER_INT_STAT

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Interpret as ER_INT_STAT

15 1211 87 43 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CMD_TO)CMD_TO 0 (CMD_CRC)CMD_CRC 0 (CMD_END_BIT)CMD_END_BIT 0 (CMD_IDX)CMD_IDX 0 (DATA_TO)DATA_TO 0 (DATA_CRC)DATA_CRC 0 (DATA_END_BIT)DATA_END_BIT 0 (CURRENT_LIMIT)CURRENT_LIMIT 0 (AUTO_CMD_12)AUTO_CMD_12 0 (ADMA)ADMA 0 (DMA)DMA

Description

Error Interrupt Status.

Fields

CMD_TO

Command Timeout Error.

CMD_CRC

Command CRC Error.

CMD_END_BIT

Command End Bit Error.

CMD_IDX

Command Index Error.

DATA_TO

Data Timeout Error.

DATA_CRC

Data CRC Error.

DATA_END_BIT

Data End Bit Error.

CURRENT_LIMIT

Current Limit Error.

AUTO_CMD_12

Auto CMD Error.

ADMA

ADMA Error.

DMA

DMA Error.

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