Maxim-Integrated /max32650 /SPI0 /CLK_CFG

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as CLK_CFG

SCALE=DIV1

Description

Register for controlling SPI clock rate.

Fields

LO	Low duty cycle control. In timer mode, reload[7:0].
HI	High duty cycle control. In timer mode, reload[15:8].
SCALE	System Clock scale factor. Scales the AMBA clock by 2^SCALE before generating serial clock. 0 (DIV1): Divide SPI Clock Frequency by 1. 1 (DIV2): Divide SPI Clock Frequency by 2. 2 (DIV4): Divide SPI Clock Frequency by 4. 3 (DIV8): Divide SPI Clock Frequency by 8. 4 (DIV16): Divide SPI Clock Frequency by 16. 5 (DIV32): Divide SPI Clock Frequency by 32. 6 (DIV64): Divide SPI Clock Frequency by 64. 7 (DIV128): Divide SPI Clock Frequency by 128. 8 (DIV256): Divide SPI Clock Frequency by 256.

Links

()