BUS_WIDTH=Mono, NUM_BITS=16BITS, CLK_POL=Normal, CLK_PHA=risingEdge, THREE_WIRE=4wire
Register for controlling SPI peripheral.
| CLK_PHA | Clock Phase. 0 (risingEdge): Data Sampled on clock rising edge. Use when in SPI Mode 0 and Mode 2 1 (fallingEdge): Data Sampled on clock falling edge. Use when in SPI Mode 1 and Mode 3 |
| CLK_POL | Clock Polarity. 0 (Normal): Normal Clock. Use when in SPI Mode 0 and Mode 1 1 (Inverted): Inverted Clock. Use when in SPI Mode 2 and Mode 3 |
| NUM_BITS | Number of Bits per character. 0 (16BITS): 16 bits per character. 1 (1BITS): 1 bits per character. 2 (2BITS): 2 bits per character. 3 (3BITS): 3 bits per character. 4 (4BITS): 4 bits per character. 5 (5BITS): 5 bits per character. 6 (6BITS): 6 bits per character. 7 (7BITS): 7 bits per character. 8 (8BITS): 8 bits per character. 9 (9BITS): 9 bits per character. 10 (10BITS): 10 bits per character. 11 (11BITS): 11 bits per character. 12 (12BITS): 12 bits per character. 13 (13BITS): 13 bits per character. 14 (14BITS): 14 bits per character. 15 (15BITS): 15 bits per character. |
| BUS_WIDTH | SPI Data width. 0 (Mono): 1 data pin. 1 (Dual): 2 data pins. 2 (Quad): 4 data pins. |
| THREE_WIRE | Three Wire mode. MOSI/MISO pin (s) shared. Only Mono mode suports Four-Wire. 0 (4wire): Use four wire mode (Mono only). 1 (3wire): Use three wire mode. |
| SS_POL | Slave Select Polarity, each Slave Select can have unique polarity. 1 (SS0_high): SS0 active high. 2 (SS1_high): SS1 active high. 4 (SS2_high): SS2 active high. 8 (SS3_high): SS3 active high. |