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Maxim-Integrated /max32650 /SPI0 /SS_TIME

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Interpret as SS_TIME

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (256)SSACT10 (256)SSACT20 (256)SSINACT

SSACT2=256, SSACT1=256, SSINACT=256

Description

Register for controlling SPI peripheral/Slave Select Timing.

Fields

SSACT1

Slave Select Pre delay 1.

0 (256): 256 system clocks between SS active and first serial clock edge.
SSACT2

Slave Select Post delay 2.

0 (256): 256 system clocks between last serial clock edge and SS inactive.
SSINACT

Slave Select Inactive delay.

0 (256): 256 system clocks between transactions.

Links

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Register Reference

https://github.com/analogdevicesinc/msdk