START=stop, OD_OUT_EN=dis, BIRQ=dis, IRQE=dis, MMEN=slave, CLKPOL=idleLo, PHASE=activeEdge, STR=complete
SPI Control Register.
| START | SPI Enable. 0 (stop): undefined 1 (start): undefined |
| MMEN | SPI Master Mode Enable. 0 (slave): undefined 1 (master): undefined |
| OD_OUT_EN | Wired OR (open drain) Enable. 0 (dis): undefined 1 (en): undefined |
| CLKPOL | Clock Polarity. 0 (idleLo): SCLK idles Low (0) after character transmission/reception. 1 (idleHi): SCLK idles High (1) after character transmission/reception. |
| PHASE | Phase Select. 0 (activeEdge): Transmit on active edge of SCLK. 1 (inactiveEdge): Transmit on inactive edge of SCLK. |
| BIRQ | Baud Rate Generator Timer Interrupt Request. 0 (dis): undefined 1 (en): undefined |
| STR | Start SPI Interrupt. 0 (complete): No operation/complete. 1 (start): Start operation. |
| IRQE | Interrupt Request Enable. 0 (dis): undefined 1 (en): undefined |