TX_FIFO_LVL=1entries, RX_DMA_EN=dis, RX_FIFO_LVL=1entries, TX_DMA_EN=dis
SPI DMA Register.
| TX_FIFO_LVL | Transmit FIFO Level. Set the number of free entries in the TxFIFO when a TxDMA request occurs. 0 (1entries): undefined 1 (2entries): undefined 2 (3entries): undefined 3 (4entries): undefined 4 (5entries): undefined 5 (6entries): undefined 6 (7entries): undefined 7 (8entries): undefined |
| TX_FIFO_CLR | Transmit FIFO Clear. 1 (clear): Start TX FIFO Clear operation. |
| TX_FIFO_CNT | Transmit FIFO Count. |
| TX_DMA_EN | Transmit DMA Enable. 0 (dis): undefined 1 (en): undefined |
| RX_FIFO_LVL | Receive FIFO Level. Sets the RX FIFO DMA request threshold. This configures the number of filled RxFIFO entries before activating an RxDMA request. 0 (1entries): undefined 1 (2entries): undefined 2 (3entries): undefined 3 (4entries): undefined 4 (5entries): undefined 5 (6entries): undefined 6 (7entries): undefined 7 (8entries): undefined |
| RX_FIFO_CLR | Receive FIFO Clear. 1 (clear): Start RX FIFO clear operation. |
| RX_FIFO_CNT | Receive FIFO Count. |
| RX_DMA_EN | Receive DMA Enable. 0 (dis): undefined 1 (en): undefined |