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Maxim-Integrated /max32650 /SPIXF /MODE_CTRL

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Interpret as MODE_CTRL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0MDCLK0 (always)NOCMD 0 (MODE_SEND)MODE_SEND

NOCMD=always

Description

SPIX Mode Control Register.

Fields

MDCLK

Mode Clocks. Number of SPI clocks needed during mode/dummy phase of fetch.
NOCMD

No Command Mode.

0 (always): Send read command every time SPI transaction is initiated.

1 (once): Send read command only once. NO read command in subsequent SPI transactions.
MODE_SEND

Mode Send.

1 (next): Send mode byte on next transaction.

Links

()

Register Reference

https://github.com/analogdevicesinc/msdk