LOCLK=16CLK, HICLK=16CLK, PGSZ=4bytes, INACT=4CLK, SSEL=slave0, IOSMPL=NODLY, MODE=mode0, SSACT=0CLK
Configuration Register.
| SSEL | Slaves Select. 0 (slave0): Slave 0 is selected. |
| MODE | Defines SPI Mode, Only valid values are 0 and 3. 0 (mode0): SPIX Mode 0. CLK Polarity = 0, CLK Phase = 0. 3 (mode3): SPIX Mode 3. CLK Polarity = 1, CLK Phase = 1. |
| PGSZ | Page Size. 0 (4bytes): 4 bytes. 1 (8bytes): 8 bytes. 2 (16bytes): 16 bytes. 3 (32bytes): 32 bytes. |
| HICLK | SCLK High Clocks. Number of system clocks that SCLK will be high when SCLK pulses are generated. 0 Correspond to 16 system clocks and, all other values defines the number of system clock taht SCLK will be held high. 0 (16CLK): 16 system clocks. 1 (1CLK): 1 system clocks. 2 (2CLK): 2 system clocks. 3 (3CLK): 3 system clocks. 4 (4CLK): 4 system clocks. 5 (5CLK): 5 system clocks. 6 (6CLK): 6 system clocks. 7 (7CLK): 7 system clocks. 8 (8CLK): 8 system clocks. 9 (9CLK): 9 system clocks. 10 (10CLK): 10 system clocks. 11 (11CLK): 11 system clocks. 12 (12CLK): 12 system clocks. 13 (13CLK): 13 system clocks. 14 (14CLK): 14 system clocks. 15 (15CLK): 15 system clocks. |
| LOCLK | SCLK low Clocks. Number of system clocks that SCLK will be low when SCLK pulses are generated. 0 correspond to 16 system clocks and, all other values defines the number of system clock taht SCLK will be held low. 0 (16CLK): 16 system clocks. 1 (1CLK): 1 system clocks. 2 (2CLK): 2 system clocks. 3 (3CLK): 3 system clocks. 4 (4CLK): 4 system clocks. 5 (5CLK): 5 system clocks. 6 (6CLK): 6 system clocks. 7 (7CLK): 7 system clocks. 8 (8CLK): 8 system clocks. 9 (9CLK): 9 system clocks. 10 (10CLK): 10 system clocks. 11 (11CLK): 11 system clocks. 12 (12CLK): 12 system clocks. 13 (13CLK): 13 system clocks. 14 (14CLK): 14 system clocks. 15 (15CLK): 15 system clocks. |
| SSACT | Slaves Select Activate Timing. 0 (0CLK): 0 sytem clocks. 1 (2CLK): 2 sytem clocks. 2 (4CLK): 4 sytem clocks. 3 (8CLK): 8 sytem clocks. |
| INACT | Slaves Select Inactive Timing. 0 (4CLK): 4 sytem clocks. 1 (6CLK): 6 sytem clocks. 2 (8CLK): 8 sytem clocks. 3 (12CLK): 12 sytem clocks. |
| IOSMPL | Sample Delay 0 (NODLY): No sample clock delay. 1 (1CLK): 1 system clocks. 2 (2CLK): 2 system clocks. 3 (3CLK): 3 system clocks. 4 (4CLK): 4 system clocks. 5 (5CLK): 5 system clocks. 6 (6CLK): 6 system clocks. 7 (7CLK): 7 system clocks. 8 (8CLK): 8 system clocks. 9 (9CLK): 9 system clocks. 10 (10CLK): 10 system clocks. 11 (11CLK): 11 system clocks. 12 (12CLK): 12 system clocks. 13 (13CLK): 13 system clocks. 14 (14CLK): 14 system clocks. 15 (15CLK): 15 system clocks. |