SSDR=output0, SIMPLE=dis, ENABLE=dis, BBMODE=dis, SCKDR=sck0, SCKFBINV=normal, SCKFB=dis, RFIFOEN=dis, TFIFOEN=dis
SPIX Controller General Controller Register.
| ENABLE | SPI Master enable. 0 (dis): Disable SPI Master, putting a reset state. 1 (en): Enable SPI Master for processing transactions. |
| TFIFOEN | Transaction FIFO Enable. 0 (dis): Disable Transaction FIFO. 1 (en): Enable Transaction FIFO. |
| RFIFOEN | Result FIFO Enable. 0 (dis): Disable Result FIFO. 1 (en): Enable Result FIFO. |
| BBMODE | Bit-Bang Mode. 0 (dis): Disable Bit-Bang Mode. 1 (en): Enable Bit-Bang Mode. |
| SSDR | This bits reflects the state of the currently selected slave select. 0 (output0): Selected Slave select output = 0. 1 (output1): Selected Slave select output = 1. |
| SCKDR | SSCLK Drive and State. 0 (sck0): SCLK is 0. 1 (sck1): SCLK is 1. |
| SDATAIN | SDIO Input Data Value. 1 (SDIO0): SDIO[0] 2 (SDIO1): SDIO[1] 4 (SDIO2): SDIO[2] 8 (SDIO3): SDIO[3] |
| BBDAT | No description available. 1 (SDIO0): SDIO[0] 2 (SDIO1): SDIO[1] 4 (SDIO2): SDIO[2] 8 (SDIO3): SDIO[3] |
| BBDATOEN | Bit Bang SDIO Output Enable. 1 (SDIO0): SDIO[0] 2 (SDIO1): SDIO[1] 4 (SDIO2): SDIO[2] 8 (SDIO3): SDIO[3] |
| SIMPLE | Simple Mode Enable. 0 (dis): Disable Simple Mode. 1 (en): Enable Simple Mode. |
| SIMPLERX | Simple Receive Enable. 1 (initSPI): Initiate SPI transaction. |
| SMPLSS | Simple Mode Slave Select. 1 (deassertSS): Deassert Slave select when SIMPLE = 1. |
| SCKFB | Enable SCLK Feedback Mode. 0 (dis): undefined 1 (en): undefined |
| SCKFBINV | SCK Invert. 0 (normal): undefined 1 (invert): undefined |