SAMPL=dis, SCKINH3=en
SPIX Controller Special Control Register.
| SAMPL | Setting this bit to a 1 enables the ability to drive SDIO outputs prior to the assertion of Slave Select. This bit must only be set when the SPIXF bus is idle and the transaction FIFO is empty. This bit is automatically cleared by hardware after the next slave select assertion. 0 (dis): Disable sample mode. 1 (en): Enable sample mode. |
| SDIO_OUT | SDIO Output Value Sample Mode 1 (SDIO0): SDIO[0] 2 (SDIO1): SDIO[1] 4 (SDIO2): SDIO[2] 8 (SDIO3): SDIO[3] |
| SDIO_OUT_EN | SDIO Output Enable Sample Mode 1 (SDIO0): SDIO[0] 2 (SDIO1): SDIO[1] 4 (SDIO2): SDIO[2] 8 (SDIO3): SDIO[3] |
| SCKINH3 | SCLK Inhibit Mode3. In SPI Mode 3, some SPI flash read timing diagrams show the last SCLK going low prior to de-assertion. The default is to support this additional falling edge of clock. When this bit is set and the device is in SPI Mode 3, the SPI clock is held high while Slave Select is de-asserted. This is to support some SPI flash write timing diagrams. 0 (en): Allow trailing SCLK low pulse prior to Slave Select de-assertion. 1 (dis): Inhibit trailing SCLK low pulse prior to Slave Select de-assertion. |