MASTER=dis, SS_CTRL=deassert, SS_IO=output, ENABLE=dis
Register for controlling SPI peripheral.
| ENABLE | SPI Enable. 0 (dis): SPI is disabled. 1 (en): SPI is enabled. |
| MASTER | Master Mode Enable. 0 (dis): SPI is Slave mode. 1 (en): SPI is Master mode. |
| SS_IO | Slave Select 0, IO direction, to support Multi-Master mode, Slave Select 0 can be input in Master mode. This bit has no effect in slave mode. 0 (output): Slave select 0 is output. 1 (input): Slave Select 0 is input, only valid if MMEN=1. |
| START | Start Transmit. 1 (start): Master Initiates a transaction, this bit is self clearing when transactions are done. If a transaction completes, and the TX FIFO is empty, the Master halts, if a transaction completes, and the TX FIFO is not empty, the Master initiates another transaction. |
| SS_CTRL | Slave Select Control. 0 (deassert): SPI de-asserts Slave Select at the end of a transaction. 1 (assert): SPI leaves Slave Select asserted at the end of a transaction. |
| SS | Slave Select, when in Master mode selects which Slave devices are selected. More than one Slave device can be selected. |