CPHA=risingEdge, THREE_WIRE=4wire, DATA_WIDTH=Mono, NUMBITS=16BITS, CPOL=normal, SSPOL=activeLow, SCLK_INV=Normal
Register for controlling SPI peripheral.
| CPHA | Clock Phase. 0 (risingEdge): Data sampled on rising edge. 1 (fallingEdge): Data sample on falling edge. |
| CPOL | Clock Polarity. 0 (normal): Normal clock. 1 (inverted): Inverted clock. |
| SCLK_INV | Invert SCLK Feedback in Master Mode. 0 (Normal): SCLK is not inverted to Line Receiver. |
| NUMBITS | Number of Bits per character. 0 (16BITS): 16 bits per character. 1 (1BITS): 1 bits per character. 2 (2BITS): 2 bits per character. 3 (3BITS): 3 bits per character. 4 (4BITS): 4 bits per character. 5 (5BITS): 5 bits per character. 6 (6BITS): 6 bits per character. 7 (7BITS): 7 bits per character. 8 (8BITS): 8 bits per character. 9 (9BITS): 9 bits per character. 10 (10BITS): 10 bits per character. 11 (11BITS): 11 bits per character. 12 (12BITS): 12 bits per character. 13 (13BITS): 13 bits per character. 14 (14BITS): 14 bits per character. 15 (15BITS): 15 bits per character. |
| DATA_WIDTH | SPI Data width. 0 (Mono): 1 data pin. 1 (Dual): 2 data pins. 2 (Quad): 4 data pins. |
| THREE_WIRE | Three Wire mode. MOSI/MISO pin (s) shared. Only Mono mode suports Four-Wire. 0 (4wire): Use four wire mode (Mono only). 1 (3wire): Use three wire mode. |
| SSPOL | Slave Select Polarity 0 (activeLow): Slave select is active low. 1 (activeHigh): Slave select is active high. |