Maxim-Integrated /max32650 /TMR0 /CN

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Interpret as CN

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (oneshot)TMODE0 (div1)PRES0 (activeHi)TPOL 0 (dis)TEN 0 (div64)PRES3 0 (dis)PWMSYNC 0 (normal)NOLHPOL 0 (normal)NOLLPOL 0 (en)PWMCKBD

NOLHPOL=normal, PWMCKBD=en, TEN=dis, PRES3=div64, PWMSYNC=dis, NOLLPOL=normal, TPOL=activeHi, PRES=div1, TMODE=oneshot

Description

Timer Control Register.

Fields

TMODE

Timer Mode.

0 (oneshot): One Shot Mode.

1 (continuous): Continuous Mode.

2 (counter): Counter Mode.

3 (pwm): PWM Mode.

4 (capture): Capture Mode.

5 (compare): Compare Mode.

6 (gated): Gated Mode.

7 (capturecompare): Capture/Compare Mode.

PRES

Prescaler. Set the Timer’s prescaler value. The prescaler divides the PCLK input to the timer and sets the Timer’s Count Clock, F_CNT_CLK = PCLK (HZ) /prescaler. The Timer’s prescaler setting is a 4-bit value with pres3:pres[2:0].

0 (div256): Divide by 256. Additionally, TMRn->cn.pres3 must be set.

0 (div1): Divide by 1.

1 (div2): Divide by 2.

2 (div4): Divide by 4.

2 (div512): Divide by 512. Additionally, TMRn->cn.pres3 must be set.

3 (div1024): Divide by 1024. Additionally, TMRn->cn.pres3 must be set.

3 (div8): Divide by 8.

4 (div16): Divide by 16.

4 (div2048): Divide by 2048. Additionally, TMRn->cn.pres3 must be set.

5 (div32): Divide by 32.

5 (div4096): Divide by 4096. Additionally, TMRn->cn.pres3 must be set.

6 (div64): Divide by 64.

7 (div128): Divide by 128.

TPOL

Timer input/output polarity bit.

0 (activeHi): Active High.

1 (activeLo): Active Low.

TEN

Timer Enable.

0 (dis): Disable.

1 (en): Enable.

PRES3

MSB of prescaler value.

0 (div1): Divide by 1.

0 (div32): Divide by 32.

0 (div16): Divide by 16.

0 (div8): Divide by 8.

0 (div4): Divide by 4.

0 (div2): Divide by 2.

0 (div128): Divide by 128.

0 (div64): Divide by 64.

1 (div4096): Divide by 4096. Additionally, TMRn->cn.pres3 must be set.

1 (div2048): Divide by 2048. Additionally, TMRn->cn.pres3 must be set.

1 (div1024): Divide by 1024. Additionally, TMRn->cn.pres3 must be set.

1 (div512): Divide by 512. Additionally, TMRn->cn.pres3 must be set.

1 (div256): Divide by 256. Additionally, TMRn->cn.pres3 must be set.

PWMSYNC

Timer PWM Synchronization Mode Enable.

0 (dis): Disable.

1 (en): Enable.

NOLHPOL

Timer PWM output 0A polarity bit.

0 (normal): Normal output polarity.

1 (invert): Inverted output polarity.

NOLLPOL

Timer PWM output 0A’ polarity bit.

0 (normal): Normal output polarity.

1 (invert): Inverted output polarity.

PWMCKBD

Timer PWM output 0A Mode Disable.

0 (en): Enable.

1 (dis): Disable.

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