RNG_IS=not_ready, RNG_I4S=not_ready, RNG_IE=dis
TRNG Control Register.
| RNG_IE | To enable IRQ generation when a new 32-bit Random number is ready. 0 (dis): Disable 1 (en): Enable |
| RNG_ISC | Clears the RNG interrupt occuring after an 128-bit random number is ready. 1 (clear): Clear the RNG interrupt. |
| RNG_I4S | This bit is set when a new 128 bit random number is ready to be read (using 4 consecutive reads of TRNG_DATA. When set, an interrupt will be generated if TRNG_CTRL.rng_ie = 1. This bit is cleared by setting TRNG_CTRL.rng_isc. 0 (not_ready): 128-bit random number not ready. 1 (ready): 128-bit random number ready. |
| RNG_IS | This bit is set when a new 32 bit random number is available in TRNG_DATA. 0 (not_ready): 32-bit random number not ready. 1 (ready): 32-bit random number ready. |
| AESKG | When enabled, the key for securing NVSRAM is generated and transferred to the secure key register automatically without user visibility or intervention. This bit is cleared by hardware once the key has been transferred to the secure key register. |