PARITY_LVL=ZERO, FLOW=dis, CLK_SEL=periph_clk, RXFLUSH=nop, PARITY_MODE=even, PARITY_EN=dis, STOP=1_stopbits, BITACC=frame, ENABLE=dis, FLOWPOL=active_low, BREAK=normal, NULLMOD=normal, TXFLUSH=nop, SIZE=5bit_data
Control Register.
| ENABLE | UART enabled, to enable UART block, it is used to drive a gated clock in order to save power consumption when UART is not used. FIFOs are flushed when UART is disabled. 0 (dis): UART disabled. FIFOs are flushed. Clock is gated off for power savings. 1 (en): UART enabled. |
| PARITY_EN | Enable/disable Parity bit (9th character). 0 (dis): No Parity 1 (en): Parity enabled as 9th bit |
| PARITY_MODE | When PARITY_EN=1, selects odd, even, Mark or Space parity. Mark parity = always 1; Space parity = always 0. 0 (even): Even parity selected. 1 (odd): Odd parity selected. 2 (mark): Mark parity selected. 3 (space): Space parity selected. |
| PARITY_LVL | Selects parity based on 1s or 0s count (when PARITY_EN=1). 0 (ZERO): Parity calculation is based on number of 0s in frame. 1 (ONE): Parity calculation is based on number of 1s in frame. |
| TXFLUSH | Flushes the TX FIFO buffer. 0 (nop): No flush operation in progress/no effect. 1 (flush): TX FIFO flush initiation or flush operation currently in progress. |
| RXFLUSH | Flushes the RX FIFO buffer. 0 (nop): No flush operation in progress/no effect. 1 (flush): RX FIFO flush initiation or flush operation currently in progress. |
| BITACC | If set, bit accuracy is selected, in this case the bit duration is the same for all the bits with the optimal accuracy. But the frame duration can have a significant deviation from the expected baudrate.If clear, frame accuracy is selected, therefore bits can have different duration in order to guarantee the minimum frame deviation. 0 (frame): Frame accuracy. 1 (bit): Bit accuracy. |
| SIZE | Selects UART character size. 0 (5bit_data): 5 bits. 1 (6bit_data): 6 bits. 2 (7bit_data): 7 bits. 3 (8bit_data): 8 bits. |
| STOP | Selects the number of stop bits that will be generated. 0 (1_stopbits): 1 stop bit. 1 (2_stopbits): 1.5 stop bits if the character size is 5, 2 stop bits for all other character sizes. |
| FLOW | Enables/disables hardware flow control. 0 (dis): HW Flow Control disabled 1 (en): HW Flow Control with RTS/CTS enabled |
| FLOWPOL | RTS/CTS polarity. 0 (active_low): RTS/CTS asserted is logic 0. 1 (active_high): RTS/CTS asserted is logic 1. |
| NULLMOD | NULL Modem Support (RTS/CTS and TXD/RXD swap). 0 (normal): Direct convention. 1 (swapped): Null Modem Mode. RTS/CTS swapped and TX/RX swapped. |
| BREAK | Break control bit. It causes a break condition to be transmitted to receiving UART. 0 (normal): Break characters are not generated. 1 (break): Break characters are sent (all the bits are at ‘0’ including start/parity/stop). |
| CLK_SEL | Baud Rate Clock Source Select. Selects the baud rate clock. 0 (periph_clk): System clock. 1 (alt_clk): Alternate 7.3727MHz internal clock. Useful in low power modes when the system clock is slow. |
| TO_CNT | RX Time Out. RX time out interrupt will occur after TO_CNT Uart characters if RX-FIFO is not empty and RX FIFO has not been read. |