Maxim-Integrated /max32657 /GCR /EVENTEN

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Interpret as EVENTEN

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DMA0)DMA0 0 (DMA1)DMA1 0 (TX)TX

Description

Event Enable Register.

Fields

DMA0

Enable DMA0 event. When this bit is set, a DMA0 event will cause an RXEV event to wake the CPU from WFE sleep mode.

DMA1

Enable DMA1 event. When this bit is set, a DMA1 event will cause an RXEV event to wake the CPU from WFE sleep mode.

TX

Enable TXEV pin event. When this bit is set, TXEV event from the CPU is output to GPIO[25].

Links

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