Regviz

Maxim-Integrated /max32657 /GCR /PCLKDIS1

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as PCLKDIS1

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Maxim-Integrated/max32657/GCR/PCLKDIS1#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (en)TRNG 0 (CRC)CRC 0 (AES)AES 0 (DMA1)DMA1 0 (WDT)WDT

TRNG=en

Description

Peripheral Clock Disable.

Fields

TRNG

TRNG Clock Disable.

0 (en): Enable.

1 (dis): Disable.
CRC

CRC Disable.
AES

AES Clock Disable
DMA1

DMA1 Clock Disable
WDT

WDT Clock Disable

Links

()

Register Reference

https://github.com/analogdevicesinc/msdk