Maxim-Integrated /max32657 /GCR /RST0

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as RST0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DMA0)DMA0 0 (WDT)WDT 0 (GPIO0)GPIO0 0 (TMR0)TMR0 0 (TMR1)TMR1 0 (TMR2)TMR2 0 (TMR3)TMR3 0 (TMR4)TMR4 0 (TMR5)TMR5 0 (UART)UART 0 (SPI)SPI 0 (I3C)I3C 0 (RTC)RTC 0 (TRNG)TRNG 0 (DMA1)DMA1 0 (SOFT)SOFT 0 (PERIPH)PERIPH 0 (SYS)SYS

Description

Reset.

Fields

DMA0

DMA Reset.

WDT

Watchdog Timer Reset.

GPIO0

GPIO0 Reset. Setting this bit to 1 resets GPIO0 pins to their default states.

TMR0

Timer0 Reset.

TMR1

Timer1 Reset.

TMR2

Timer2 Reset.

TMR3

Timer3 Reset.

TMR4

Timer4 Reset.

TMR5

Timer5 Reset.

UART

UART Reset.

SPI

SPI Reset.

I3C

I3C Reset.

RTC

Real Time Clock Reset.

TRNG

TRNG Reset.

DMA1

DMA1 Reset.

SOFT

Soft Reset. Setting this bit to 1 resets everything except the CPU and the watchdog timer.

PERIPH

Peripheral Reset. Setting this bit to 1 resets all peripherals. The CPU core, the watchdog timer, and all GPIO pins are unaffected by this reset.

SYS

System Reset. Setting this bit to 1 resets the CPU core and all peripherals, including the watchdog timer.

Links

()