Maxim-Integrated /max32657 /GPIO0 /PADCTRL

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Interpret as PADCTRL

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (impedance)ALL

ALL=impedance

Description

GPIO Pad Control. Each bit in this register configures the pad for the associated GPIO pin in this port.

Fields

ALL

The two bits in GPIO_PADCTRL0 and GPIO_PADCTRL1 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode.

0 (impedance): High Impedance.

1 (pu): Weak pull-up mode.

2 (pd): weak pull-down mode.

Links

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