Maxim-Integrated /max32657 /I3C0 /CONT_CTRL0

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Interpret as CONT_CTRL0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (OFF)EN0 (TO_DIS)TO_DIS 0 (OFF)HKEEP 0 (OD_STOP)OD_STOP 0 (1_FCLK)PP_BAUD0 (0_FCLK)PP_ADD_LBAUD 0OD_LBAUD0 (OD_HP)OD_HP 0PP_SKEW 0I2C_BAUD

PP_BAUD=1_FCLK, PP_ADD_LBAUD=0_FCLK, EN=OFF, HKEEP=OFF

Description

Controller Control 0 (Configuration) Register.

Fields

EN

I3C Device Enable.

0 (OFF): Off.

1 (ON): On.

2 (CAP): I23 Bug Target with secondary controller capability.

TO_DIS

Disable Timeout error.

HKEEP

High-keepr implementation.

0 (OFF): No high-keeper support.

1 (ON_CHIP): On-chip high-keeper support.

2 (EXT_SDA): External high-keeper support for SDA.

3 (EXT_SCL_SDA): External high-keeper support for SCL and SDA.

OD_STOP

Use open-drain speed for STOP.

PP_BAUD

SCL Frequency for push-pull drive.

0 (1_FCLK): SCL High Period is one FCLK Period.

1 (2_FCLK): SCL High Period is two FLCK Periods.

2 (3_FCLK): SCL High Period is three FCLK Period.

3 (4_FCLK): SCL High Period is four FCLK Period.

4 (5_FCLK): SCL High Period is five FCLK Period.

5 (6_FCLK): SCL High Period is six FCLK Period.

6 (7_FCLK): SCL High Period is seven FCLK Period.

7 (8_FCLK): SCL High Period is eight FCLK Period.

8 (9_FCLK): SCL High Period is nine FCLK Period.

9 (10_FCLK): SCL High Period is ten FCLK Period.

10 (11_FCLK): SCL High Period is eleven FCLK Period.

11 (12_FCLK): SCL High Period is twelve FCLK Period.

12 (13_FCLK): SCL High Period is thirteen FCLK Period.

13 (14_FCLK): SCL High Period is fourteen FCLK Period.

14 (15_FCLK): SCL High Period is fifthteen FCLK Period.

15 (16_FCLK): SCL High Period is sixteen FCLK Period.

PP_ADD_LBAUD

Number of FCLK periods to add to the base of SCL low period.

0 (0_FCLK): Adds zero FCLK periods to the SCL low period.

1 (1_FCLK): Adds one FCLK period to the SCL low period.

2 (2_FCLK): Adds two FCLK periods to the SCL low period.

3 (3_FCLK): Adds three FCLK periods to the SCL low period.

4 (4_FCLK): Adds four FCLK periods to the SCL low period.

5 (5_FCLK): Adds five FCLK periods to the SCL low period.

6 (6_FCLK): Adds six FCLK periods to the SCL low period.

7 (7_FCLK): Adds seven FCLK periods to the SCL low period.

8 (8_FCLK): Adds eight FCLK periods to the SCL low period.

9 (9_FCLK): Adds nine FCLK periods to the SCL low period.

10 (10_FCLK): Adds ten FCLK periods to the SCL low period.

11 (11_FCLK): Adds eleven FCLK periods to the SCL low period.

12 (12_FCLK): Adds twelve FCLK periods to the SCL low period.

13 (13_FCLK): Adds thirteen FCLK periods to the SCL low period.

14 (14_FCLK): Adds fourteen FCLK periods to the SCL low period.

15 (15_FCLK): Adds fifthteen FCLK periods to the SCL low period.

OD_LBAUD

Number of PP_BAUD periods minus 1 to make one SCL low period for I3C open-dran periods.

OD_HP

Controls SCL high period for I3C oepn-drain operation.

PP_SKEW

Number of FCLK periods to delay the SDA value change from the SCL edge for I3C push-pull operation.

I2C_BAUD

Detyermines SCL high and low pweriods for I2C mode, in units of OD_BAUD period.

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