EN=dis, CONT_MODE=dis, TS_CTRL=DEASSERT, TS_IO=output
Register for controlling SPI peripheral.
| EN | SPI Enable. 0 (dis): SPI is disabled. 1 (en): SPI is enabled. |
| CONT_MODE | Controller Mode Enable. 0 (dis): SPI is Target mode. 1 (en): SPI is Controller mode. |
| TS_IO | Target Select 0, IO direction, to support Multi-Controller mode,Target Select 0 can be input in Controller mode. This bit has no effect in target mode. 0 (output): Target select 0 is output. 1 (input): Target Select 0 is input, only valid if MMEN=1. |
| START | Start Transmit. 1 (start): Controller Initiates a transaction, this bit is self clearing when transactions are done. If a transaction cimpletes, and the TX FIFO is empty, the Controller halts, if a transaction completes, and the TX FIFO is not empty, the Controller initiates another transaction. |
| TS_CTRL | Start Select Control. Used in Controller mode to control the behavior of the Target Select signal at the end of a transaction. 0 (DEASSERT): SPI De-asserts Target Select at the end of a transaction. 1 (ATSERT): SPI leaves Target Select asserted at the end of a transaction. |
| TS_ACTIVE | Target Select, when in Controller mode selects which Target devices are selected. More than one Target device can be selected. 1 (TS0): TS0 is selected. 2 (TS1): TS1 is selected. 4 (TS2): TS2 is selected. |