Maxim-Integrated /max32657 /SPI /STATUS

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as STATUS

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (not)BUSY

BUSY=not

Description

SPI Status register.

Fields

BUSY

SPI active status. In Controller mode, set when transaction starts, cleared when last bit of last character is acted upon and Target Select de-assertion would occur. In Target mode, set when Target Select is asserted, cleared when Target Select is de-asserted. Not used in Timer mode.

0 (not): SPI not active.

1 (active): SPI active.

Links

()