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Maxim-Integrated /max32657 /SPI /TSTIME

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Interpret as TSTIME

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (256)PRE0 (256)POST0 (256)INACT

POST=256, PRE=256, INACT=256

Description

Register for controlling SPI peripheral/Target Select Timing.

Fields

PRE

Target Select Pre delay 1.

0 (256): 256 system clocks between TS active and first serial clock edge.
POST

Target Select Post delay 2.

0 (256): 256 system clocks between last serial clock edge and TS inactive.
INACT

Target Select Inactive delay.

0 (256): 256 system clocks between transactions.

Links

()

Register Reference

https://github.com/analogdevicesinc/msdk