CLK_SEL=PERIPHERAL_CLOCK, CHAR_SIZE=5bits
Control register
| RX_THD_VAL | This field specifies the depth of receive FIFO for interrupt generation (value 0 and > 16 are ignored) |
| PAR_EN | Parity Enable |
| PAR_EO | when PAREN=1 selects odd or even parity odd is 1 even is 0 |
| PAR_MD | Selects parity based on 1s or 0s count (when PAREN=1) |
| CTS_DIS | CTS Sampling Disable |
| TX_FLUSH | Flushes the TX FIFO buffer. This bit is automatically cleared by hardware when flush is completed. |
| RX_FLUSH | Flushes the RX FIFO buffer. This bit is automatically cleared by hardware when flush is completed. |
| CHAR_SIZE | Selects UART character size 0 (5bits): 5 bits 1 (6bits): 6 bits 2 (7bits): 7 bits 3 (8bits): 8 bits |
| STOPBITS | Selects the number of stop bits that will be generated |
| HFC_EN | Enables/disables hardware flow control |
| RTS_NEG | The condition to negate RTS in HFC mode. |
| CLK_EN | Baud clock enable |
| CLK_SEL | To select the UART clock source for the UART engine (except APB registers). Secondary clock (used for baud rate generator) can be asynchronous from APB clock. 0 (PERIPHERAL_CLOCK): APB Clock. 1 (CLK1): IBRO clock. |
| CLK_RDY | Baud clock Ready read only bit |
| CLK_GATE | UART Clock Auto Gating mode |