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Maxim-Integrated /max32660 /GCR /MEM_CTRL

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Interpret as MEM_CTRL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0FWS0 (active)RAM0_LS 0 (active)RAM1_LS 0 (active)RAM2_LS 0 (active)RAM3_LS 0 (active)ICACHE_RET

RAM0_LS=active, RAM1_LS=active, RAM3_LS=active, RAM2_LS=active, ICACHE_RET=active

Description

Memory Clock Control Register.

Fields

FWS

Flash Wait State. These bits define the number of wait-state cycles per Flash data read access. Minimum wait state is 2.
RAM0_LS

System RAM 0 Light Sleep Mode.

0 (active): Memory is active.

1 (light_sleep): Memory is in Light Sleep mode.
RAM1_LS

System RAM 1 Light Sleep Mode.

0 (active): Memory is active.

1 (light_sleep): Memory is in Light Sleep mode.
RAM2_LS

System RAM 2 Light Sleep Mode.

0 (active): Memory is active.

1 (light_sleep): Memory is in Light Sleep mode.
RAM3_LS

System RAM 3 Light Sleep Mode.

0 (active): Memory is active.

1 (light_sleep): Memory is in Light Sleep mode.
ICACHE_RET

ICache RAM Light Sleep Mode.

0 (active): Memory is active.

1 (light_sleep): Memory is in Light Sleep mode.

Links

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Register Reference

https://github.com/analogdevicesinc/msdk