Maxim-Integrated /max32660 /GCR /RST0

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Interpret as RST0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DMA)DMA 0 (WDT0)WDT0 0 (GPIO0)GPIO0 0 (TIMER0)TIMER0 0 (TIMER1)TIMER1 0 (TIMER2)TIMER2 0 (UART0)UART0 0 (UART1)UART1 0 (SPI0)SPI0 0 (SPI1)SPI1 0 (I2C0)I2C0 0 (RTC)RTC 0 (SOFT)SOFT 0 (PERIPH)PERIPH 0 (SYSTEM)SYSTEM

Description

Reset.

Fields

DMA

DMA Reset.

WDT0

Watchdog Timer Reset.

GPIO0

GPIO0 Reset. Setting this bit to 1 resets GPIO0 pins to their default states.

TIMER0

Timer0 Reset. Setting this bit to 1 resets Timer 0 blocks.

TIMER1

Timer1 Reset. Setting this bit to 1 resets Timer 1 blocks.

TIMER2

Timer2 Reset. Setting this bit to 1 resets Timer 2 blocks.

UART0

UART0 Reset. Setting this bit to 1 resets all UART 0 blocks.

UART1

UART1 Reset. Setting this bit to 1 resets all UART 1 blocks.

SPI0

SPI0 Reset. Setting this bit to 1 resets all SPI 0 blocks.

SPI1

SPI1 Reset. Setting this bit to 1 resets all SPI 1 blocks.

I2C0

I2C0 Reset.

RTC

Real Time Clock Reset.

SOFT

Soft Reset.Write 1 to perform a Soft Reset. A soft reset performs a Peripheral Reset and also resets the GPIO peripheral but does not reset the CPU or Watchdog Timer.

PERIPH

Peripheral Reset. Setting this bit to 1 resets all peripherals. The CPU core, the watchdog timer, and all GPIO pins are unaffected by this reset.

SYSTEM

System Reset. Setting this bit to 1 resets the CPU core and all peripherals, including the watchdog timer.

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