TXFSH=not_flushed, TX_READY_MODE=en
Transmit Control Register 0.
| TXPRELD | Transmit FIFO Preaload Mode. Setting this bit will allow for high speed application to preload the transmit FIFO prior to Slave Address Match. |
| TX_READY_MODE | Transmit FIFO Ready Manual Mode. 0 (en): HW control of I2CTXRDY enabled. 1 (dis): HW control of I2CTXRDY disabled. |
| TXFSH | Transmit FIFO Flush. This bit is automatically cleared to 0 after the operation. 0 (not_flushed): FIFO not flushed. 1 (flush): Flush TX_FIFO. |
| TXTH | Transmit FIFO Threshold. These bits define the TX_FIFO interrupt threshold. |