SS_POL=SS0_low, DATA_WIDTH=Mono, NUM_BITS=0, THREE_WIRE=dis, CLK_POL=Normal, CLK_PHA=Rising_Edge
Register for controlling SPI peripheral.
| CLK_PHA | Clock Phase. 0 (Rising_Edge): Data Sampled on clock rising edge. Use when in SPI Mode 0 and Mode 2 1 (Falling_Edge): Data Sampled on clock falling edge. Use when in SPI Mode 1 and Mode 3 |
| CLK_POL | Clock Polarity. 0 (Normal): Normal Clock. Use when in SPI Mode 0 and Mode 1 1 (Inverted): Inverted Clock. Use when in SPI Mode 2 and Mode 3 |
| NUM_BITS | Number of Bits per character. 0 (0): 16 bits per character. |
| DATA_WIDTH | SPI Data width. 0 (Mono): 1 data pin. 1 (Dual): 2 data pins. 2 (Quad): 4 data pins. |
| THREE_WIRE | Three Wire mode. MOSI/MISO pin (s) shared. Only Mono mode suports Four-Wire. 0 (dis): Use four wire mode (Mono only). 1 (en): Use three wire mode. |
| SS_POL | Slave Select Polarity, each Slave Select can have unique polarity. 0 (SS0_low): SS1 active low. 1 (SS0_high): SS0 active high. |