RX_DMA_EN=disable, TX_FIFO_CLR=complete, TX_FIFO_LVL=entry1, TX_DMA_EN=disable, RX_FIFO_LVL=entry1, RX_FIFO_CLR=complete
SPI DMA Register.
| TX_FIFO_LVL | Transmit FIFO Level. Set the number of free entries in the TxFIFO when a TxDMA request occurs. 0 (entry1): undefined 1 (entries2): undefined 2 (entries3): undefined 3 (entries4): undefined 4 (entries5): undefined 5 (entries6): undefined 6 (entries7): undefined 7 (entries8): undefined |
| TX_FIFO_CLR | Transmit FIFO Clear. 0 (complete): No operation/complete. 1 (start): Start operation. |
| TX_FIFO_CNT | Transmit FIFO Count. |
| TX_DMA_EN | Transmit DMA Enable. 0 (disable): undefined 1 (enable): undefined |
| RX_FIFO_LVL | Receive FIFO Level. Sets the RX FIFO DMA request threshold. This configures the number of filled RxFIFO entries before activating an RxDMA request. 0 (entry1): undefined 1 (entries2): undefined 2 (entries3): undefined 3 (entries4): undefined 4 (entries5): undefined 5 (entries6): undefined 6 (entries7): undefined 7 (entries8): undefined |
| RX_FIFO_CLR | Receive FIFO Clear. 0 (complete): No operation/complete. 1 (start): Start operation. |
| RX_FIFO_CNT | Receive FIFO Count. |
| RX_DMA_EN | Receive DMA Enable. 0 (disable): undefined 1 (enable): undefined |