ENABLE=dis, PARITY_LVL=1, FLOW=dis, BREAK=DIS, SIZE=5, NULLMOD=DIS, PARITY_MODE=Even, CLK_SEL=SYSTEM, FLOWPOL=0, STOP=1, BITACC=FRAME, PARITY_EN=dis
Control Register.
| ENABLE | UART enabled, to enable UART block, it is used to drive a gated clock in order to save power consumption when UART is not used. FIFOs are flushed when UART is disabled. 0 (dis): UART disabled. FIFOs are flushed. Clock is gated off for power savings. 1 (en): UART enabled. |
| PARITY_EN | Enable/disable Parity bit (9th character). 0 (dis): No Parity 1 (en): Parity enabled as 9th bit |
| PARITY_MODE | When PARITY_EN=1, selects odd, even, Mark or Space parity. Mark parity = always 1; Space parity = always 0. 0 (Even): Even parity selected. 1 (ODD): Odd parity selected. 2 (MARK): Mark parity selected. 3 (SPACE): Space parity selected. |
| PARITY_LVL | Selects parity based on 1s or 0s count (when PARITY_EN=1). 0 (1): Parity calculation is based on number of 1s in frame. 1 (0): Parity calculation is based on number of 0s in frame. |
| TXFLUSH | Flushes the TX FIFO buffer. |
| RXFLUSH | Flushes the RX FIFO buffer. |
| BITACC | If set, bit accuracy is selected, in this case the bit duration is the same for all the bits with the optimal accuracy. But the frame duration can have a significant deviation from the expected baudrate.If clear, frame accuracy is selected, therefore bits can have different duration in order to guarantee the minimum frame deviation. 0 (FRAME): Frame accuracy. 1 (BIT): Bit accuracy. |
| SIZE | Selects UART character size. 0 (5): 5 bits. 1 (6): 6 bits. 2 (7): 7 bits. 3 (8): 8 bits. |
| STOP | Selects the number of stop bits that will be generated. 0 (1): 1 stop bit. 1 (1_5): 1.5 stop bits. |
| FLOW | Enables/disables hardware flow control. 0 (dis): HW Flow Control disabled 1 (en): HW Flow Control with RTS/CTS enabled |
| FLOWPOL | RTS/CTS polarity. 0 (0): RTS/CTS asserted is logic 0. 1 (1): RTS/CTS asserted is logic 1. |
| NULLMOD | NULL Modem Support (RTS/CTS and TXD/RXD swap). 0 (DIS): Direct convention. 1 (EN): Null Modem Mode. |
| BREAK | Break control bit. It causes a break condition to be transmitted to receiving UART. 0 (DIS): Break characters are not generated. 1 (EN): Break characters are sent(all the bits are at ‘0’ including start/parity/stop). |
| CLK_SEL | Baud Rate Clock Source Select. Selects the baud rate clock. 0 (SYSTEM): System clock. 1 (ALTERNATE): Alternate 7.3727MHz internal clock. Useful in low power modes when the system clock is slow. |
| TO_CNT | RX Time Out. RX time out interrupt will occur after RXTO Uart characters if RX-FIFO is not empty and RX FIFO has not been read. |