Maxim-Integrated /max32660 /UART0 /STAT

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Interpret as STAT

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TX_BUSY)TX_BUSY 0 (RX_BUSY)RX_BUSY 0 (PARITY)PARITY 0 (BREAK)BREAK 0 (RX_EMPTY)RX_EMPTY 0 (RX_FULL)RX_FULL 0 (TX_EMPTY)TX_EMPTY 0 (TX_FULL)TX_FULL 0RX_NUM0TX_NUM0 (RX_TO)RX_TO

Description

Status Register.

Fields

TX_BUSY

Read-only flag indicating the UART transmit status.

RX_BUSY

Read-only flag indicating the UARTreceiver status.

PARITY

9th Received bit state. This bit identifies the state of the 9th bit of received data. Only available for UART_CTRL.SIZE[1:0]=3.

BREAK

Received BREAK status. BREAKS is cleared when UART_STAT register is read. Received data input is held in spacing (logic 0) state for longer than a full word transmission time (that is, the total time of Start bit + data bits + Parity + Stop bits).

RX_EMPTY

Read-only flag indicating the RX FIFO state.

RX_FULL

Read-only flag indicating the RX FIFO state.

TX_EMPTY

Read-only flag indicating the TX FIFO state.

TX_FULL

Read-only flag indicating the TX FIFO state.

RX_NUM

Indicates the number of bytes currently in the RX FIFO.

TX_NUM

Indicates the number of bytes currently in the TX FIFO.

RX_TO

RX Timeout status.

Links

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