STATE=INT
Invalidate All Registers.
| BITERR | Bit Error Indicator. When this bit is set the inconsistency occurs between the transmitted and the received bit in CAN FD frame. |
| CRCERR | Cyclic Redundancy Check Error indicator. This indicates that calculated CRC is different from received in CAN FD frame |
| FRMERR | Form Error indicator. This bit indicates, that a fixed form bit field contains at least one illegal bit in Data phase of CAN FD frame with the BRS bit set |
| STFERR | Stuff Error Indicator. This bit indicates stuff error occurred in Data phase in CAN FD frame with the BRS bit set |
| PEE | Protocol Exception Event indicator. Indicates that core detects recessive state on res position and enter to Bus integration state. |
| STATE | Operation state. 0 (INT): Waiting for 11 recessive bit after reset or bus off 1 (IDLE): Waiting for Start of Frame. 2 (RX): Node operating as Receiver. 3 (TX): Node operating as Transmitter. |