IBRO_VS=Vcor, ERFO_RDY=not, IPO_DIV=DIV1, SYSCLK_RDY=busy, SYSCLK_DIV=div1, ERFO_EN=dis
Clock Control.
| SYSCLK_DIV | Prescaler Select. This 3 bit field sets the system operating frequency by controlling the prescaler that divides the output of the PLL0. 0 (div1): Divide by 1. 1 (div2): Divide by 2. 2 (div4): Divide by 4. 3 (div8): Divide by 8. 4 (div16): Divide by 16. 5 (div32): Divide by 32. 6 (div64): Divide by 64. 7 (div128): Divide by 128. |
| SYSCLK_SEL | Clock Source Select. This 3 bit field selects the source for the system clock. 2 (ERFO): The external 32 MHz input is used for the system clock. 3 (INRO): 8 kHz LIRC is used for the system clock. 4 (IPO): The internal 100 MHz oscillator is used for the system clock. 5 (IBRO): The internal 7.3725 MHz oscillator is used for the system clock. 6 (ERTCO): External 32 kHz input is used for the system clock. 7 (EXTCLK): External clock input is used for the system clock. |
| SYSCLK_RDY | Clock Ready. This read only bit reflects whether the currently selected system clock source is running. 0 (busy): Switchover to the new clock source (as selected by CLKSEL) has not yet occurred. 1 (ready): System clock running from CLKSEL clock source. |
| IPO_DIV | HIRC96M Source Clock Divider. 0 (DIV1): Div 1 1 (DIV2): Div 2 2 (DIV4): Div 4 3 (DIV8): Div 8 |
| ERFO_EN | 32 MHz Crystal Oscillator Enable. 0 (dis): Is Disabled. 1 (en): Is Enabled. |
| IPO_EN | 100 MHz Clock Enable. |
| IBRO_EN | 7.3725 MHz Clock Enable. |
| IBRO_VS | 7.3725 MHz High Frequency Internal Reference Clock Voltage Select. This register bit is used to select the power supply to the IBRO. 0 (Vcor): VCore Supply 1 (1V): Dedicated 1V regulated supply. |
| ERFO_RDY | 32 MHz Oscillator Ready 0 (not): Is not Ready. 1 (ready): Is Ready. |
| ERTCO_RDY | 32 kHz Crystal Oscillator Ready |
| IPO_RDY | 100 MHz Clock Ready. |
| IBRO_RDY | 7.3725 MHz HIRC Ready. |
| INRO_RDY | 8 kHz Low Frequency Reference Clock Ready. |
| EXTCLK_RDY | External Clock GPIO0_28 AF2 Ready. Clock is ready when AF2 is enabled for GPIO0_28 |