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Maxim-Integrated /max32662 /GCR /MEMCTRL

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Interpret as MEMCTRL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0FWS0 (RAMWS_EN)RAMWS_EN 0 (RAM0LS_EN)RAM0LS_EN 0 (RAM1LS_EN)RAM1LS_EN 0 (RAM2LS_EN)RAM2LS_EN 0 (RAM3LS_EN)RAM3LS_EN 0 (ICC0LS_EN)ICC0LS_EN 0 (ROMLS_EN)ROMLS_EN

Description

Memory Clock Control Register.

Fields

FWS

Flash Wait State. These bits define the number of wait-state cycles per Flash data read access. Minimum wait state is 2.
RAMWS_EN

System RAM Wait State enable.
RAM0LS_EN

System RAM 0 Light Sleep mode.
RAM1LS_EN

System RAM 1 Light Sleep mode.
RAM2LS_EN

System RAM 2 Light Sleep mode.
RAM3LS_EN

System RAM 3 Light Sleep mode.
ICC0LS_EN

Internal Cache Controller RAM Light Sleep mode.
ROMLS_EN

ROM Light Sleep mode.

Links

()

Register Reference

https://github.com/analogdevicesinc/msdk