Regviz

Maxim-Integrated /max32662 /GCR /PCLKDIS1

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as PCLKDIS1

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Maxim-Integrated/max32662/GCR/PCLKDIS1#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TRNG)TRNG 0 (WDT)WDT 0 (CAN)CAN 0 (AES)AES 0 (AES_KEY)AES_KEY 0 (I2S)I2S

Description

Peripheral Clock Disable.

Fields

TRNG

TRNG Clock Disable.
WDT

Watchdog Timer 0 Disable.
CAN

CAN Clock Disable.
AES

AES Clock Disable.
AES_KEY

AES Keys Clock Disable.
I2S

I2S Clock Disable.

Links

()

Register Reference

https://github.com/analogdevicesinc/msdk