RAM0RET_EN=dis, RAM3RET_EN=dis, RAM2RET_EN=dis, OVR=0_9V, RETREG_EN=dis, BG_DIS=on, RAM1RET_EN=dis, VCORE_DET_BYPASS=dis, FVDD_EN=dis
Low Power Control Register.
| RAM0RET_EN | System RAM 0 retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. 0 (dis): Disable Ram Retention. 1 (en): Enable System RAM 0 retention. |
| RAM1RET_EN | System RAM 1 retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. 0 (dis): Disable Ram Retention. 1 (en): Enable System RAM 1 retention. |
| RAM2RET_EN | System RAM 2 retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. 0 (dis): Disable Ram Retention. 1 (en): Enable System RAM 2 retention. |
| RAM3RET_EN | System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. 0 (dis): Disable Ram Retention. 1 (en): Enable System RAM 3 retention. |
| OVR | Operating Voltage Range. The Operating Voltage Range bits (OVR) determine the operating range for VCORE domain. 0 (0_9V): 0.9V 1 (1_0V): 1.0V 2 (1_1V): 1.1V |
| VCORE_DET_BYPASS | Block Auto Detect. Prevent the power sequencer from taking time to detect whether an external power source exists on the VCORE pin. Should always be set to 1 if VCORE is not provided from an external source. 0 (dis): Disable auto detection. 1 (en): Enable auto detection. |
| FVDD_EN | Flash VDD Enable. FOrce the flash VDD to remain enabled during LP modes. 0 (dis): Flash VDDIO Not Forced. 1 (en): Flash VDDIO Force on. |
| RETREG_EN | Retention Regulator Enable. This bit controls the retention regulator in BACKUP mode. This bit should be 1 all the time if user wants to use retention regulator. 0 (dis): Disable. 1 (en): Enable. |
| STORAGE_EN | STORAGE mode enable. |
| FASTWK_EN | Fast Wake-Up Mode. This bit enables fast wake-up from DeepSleep mode. |
| BG_DIS | Bandgap OFF. This controls the System Bandgap in DeepSleep mode. 0 (on): Bandgap is always ON. 1 (off): Bandgap is OFF in DeepSleep mode (default). |
| VCOREPOR_DIS | VCORE Power-On Reset Monitor Disable. This bit controls the Power-On Reset monitor on VDDC supply in DeepSleep and BACKUP mode. |
| LDO_DIS | Disable Main LDO. This bit initializes to 1 until the power sequencer determines that no external power source exists on the VCORE pin. At that time, this bit is automatically cleared to 0. If an external power source is detected on the VCORE pin, then this bit will remain at 1. |
| VCORE_EXT | Use external VCORE for 1V supply. |
| VCOREMON_DIS | VCORE Monitor Disable. This bit controls the power monitor on the VCORE supply in all operating modes. |
| VDDAMON_DIS | VDDA Monitor Disable. This bit controls the power monitor on the Analog supply in all operating modes. |
| PORVDDMON_DIS | VCORE Power-On Reset Monitor Disable. This bit controls the Power-On Reset monitor on VCORE supply in all operating modes. |
| VBBMON_DIS | VDDA Monitor Disable. This bit controls the power monitor on the Analog supply in all operating modes. |
| INRO_EN | Allow LIRC80K to remain on in all Power modes. If STORAGE is set, this bit has no effect. |
| ERTCO_EN | Allow LIRC32K to remain on in all Power modes. If STORAGE is set, this bit has no effect. |